
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort? Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read-to-Write-to-Read ( OE Controlled) (2)
t CYC2
CLK
CE 0
t CH2
t CL2
CE 1
t SC
t SB
t HC
t HB
LB , UB
t SW t HW
R/ W
t SW t HW
(3)
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
t SA
t HA
t SD
t HD
DATA IN
DATA OUT
(1)
t CD2
Qn
t OHZ
(4)
Dn + 2
Dn + 3
t CKLZ
t CD2
Qn + 4
OE
READ
WRITE
READ
5649 drw 12
,
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CNTLD = V IL ; CNTINC , CNTRST , MRST , MKLD , MKRD and CNTRD = V IH .
3. Addresses do not have to be accessed sequentially since CNTLD = V IL constantly loads the address on the rising edge of the CLK;
numbers are for reference use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Read with Address Counter Advance (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
An
t SCLD t HCLD
CNTLD
t SCLD t HCLD
CNTINC
t CD2
t SCLD t HCLD
DATA OUT
Qx - 1 (2)
Qx
Qn
Qn + 1
Qn + 2 (2)
Qn + 3
,
t DC
NOTES:
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5649 drw 13
1. CE 0 , LB and UB = V IL ; CE 1 , CNTRST , MRST , MKLD , MKRD and CNTRD = V IH .
2. If there is no address change via CNTLD = V IL (loading a new address) or CNTINC = V IL (advancing the address), i.e. CNTLD = V IH and CNTINC = V IH , then
the data output remains constant for subsequent clocks.
16